Magnetic core matrix



Dec. 10, 1963' w s 3,114,133

MAGNETIC CORE MATRIX Filed hug. 15, 1960 L 2 Sheets-Sheet 1 COLUMN 1COLUMN 2 OOLUNN 3' COLLIN 4 INVENTOR GERALD N. WEST BY%44,%M

ATTORNEY Dec. 10, 1963- G. N. WEST MAGNETIC CORE MATRIX 2 Sheets-Sheet 2Filed Aug. 15. 1960 00mm 2 commas ',n

COUMN 4 FIG.

FIG. 1b

series to a current driver.

United States Patent 3,114,133 MAGNETIC CORE MATRIX Gerald N. West,Endwell, N.Y., assign'or to International Business Machines Corporation,New York, N.Y., a corporation of New York Filed Aug. 15, 1960, Ser- No.49,647 8 Claims. (Cl. 340-166) This invention relates to magnetic corematrices and more particularly to an improved means for selecting aparticula core in a matrix.

In the prior art, bidirectional or two coordinate matrices are commonlyemployed; such matrices generally comprise binary elements having twostable states of energization such as magnetic cores or ferroelectriccapacitors. The binary elements may be considered to be arranged in rowsand columns and a plurality of current carrying or drive lines passthrough the rows and columns of elements, that is, the drive lines inthe rows cross the drive lines in the columns and a binary element islocated at each intersection. To energize any one of the elements in amatrix, it is necessary to coincidentally energize a drive line in oneof the rows and a drive line in one of the columns. The magnitude of thecurrent at the intersection of the drive lines which are energized issufiicient to drive the element located at said intersection.

In the prior art type of matrices in which coincident currents areutilized to cause the binary elements to shift from one to the other oftheir stable states, it is necessary that the elements have rectilinearhysteresis groups.

Accordingly, it is a principal object of this invention to provide animproved means for'selecting a particular binary element in a matrix.

It is another object of this invention to provide a means of selecting abinary element other than by energizing the element by coincidence oranticoincidence.

It is another object of this invention to provide a magnetic core matrixin which the cores of the matrix need not necessarily have rectilinearhysteresis loops.

It is yet another object of this invention to provide a matrix in whicha minimum number of current driver means are employed.

According to a preferred embodiment of the present invention, a matrixcomprising a plurality of magnetic cores arranged in a plurality ofgroups are employed; for simplicity in description, the cores areconsidered to form rows and columns. Each of the cores has wound thereona primary or input winding, a secondary winding or output winding and acontrol winding. The primary winding on each of the cores in a row isconnected in The control windings of cores in a column are connected inparallel to a gating means which selectively completes an electricalcircuit for, or open circuits the associated control windings. Thegating means are normally closed, therefore, maximum current in theprimary winding is coupled to the associated control windings and aminimum current is coupled to the associated secondary winding.

To select a core, an address decoder activates a particular currentdriver for providing current to one of the rows of cores and the addressdecoder opens a gating means for a column of cores. When the gatingmeans are opened, the control windings connected thereto are opencircuited and a minimum current from the primary winding is coupled tothe associated control winding and a maximum current is coupled to thesecondary winding. Therefore, only in the core positioned at thecoordinate of the, selected row and column is a maximum current coupledfrom the primary to the secondary winding.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments 3,114,133 Patented Dec. 10, 1963 ofthe invention, as illustrated in the accompanying drawings.

In the drawings:

FIG. 1 shows a matrix in accordance with the invention;

FIG. la shows the termination of the secondary windings of FIG. 1;

FIG. 1b shows a modification of the termination of FIG. la.

FIG. 1 shows a matrix 11 according to the invention. A .relativelysimple form of a single plane matrix is shown for purposes offacilitating the explanation of the operation of the invention. It will,however, be appreciated that the size of the matrix and the number ofcores used are essentially unlimited. Matrix'll comprises sixteenmagnetic cores arranged in a two coodinate system or, more specifically,in four rows and four columns. The rows of cores are designatedalphabetically as rows A, B, C and D; the columns of cores aredesignated as columns 1, 2, 3, 4; each core may be designated by itscoordinate, for example, core 1A is positioned at the intersection ofcolumn 1 and row A.

Each of the cores in matrix 11 includes a primary winding NP, secondarywinding NS and a control winding NC for purposes to be explained morefully hereinbelow. In FIG. 1a, only the windings on core 1A are letteredsince the corresponding designation of the windings on the other coresof the matrix are readily apparent. A group of current carrying or drivelines 13, 14, 15 and 16 are each serially connected to the primarywinding NP of the cores in rows A, B, C and D respectively for providingan input to the cores. Current amplifiers or drivers 23, 24, 25 and 26,of any suitable known type, and capable of providing a fairly constantcurrent, are connected to drive lines 13, 14, 15 and 16, respectively.

The control windings NC of the cores in the columns 1, 2, 3 and 4 areconnected to commonlines 31, 32, 33 and 34, respectively. The controlwindings of cores in a column are thus connected in parallel withrespect to one another. One terminal of each of lines 31, 32, 33 and 34is connected to ground reference and the other terminals of lines 31,32, 33 and 34 are connected to gating stages 41, 42, 43 and 44,respectively.

Each of the electrical paths for the control windings is similar. Forexample, with reference to line 31 and core 1A, the electrical path maybe traced from ground reference through line 31, the control winding NCof core 1A, a diode 45, back to line 31 and gate 41 to ground, as willbe explained hereinbelow.

Gating stages 41-44 are each connected to an address decoder 69 of anysuitable known type which is adapted to change the machine address formsto a matrix format in order to select one out of n gates in onedimension for one character and one out of n drivers in a seconddimension for a second character.

Each of gating stages or gates 41-44 comprises a pair of transistors 51and 55. Each of the gates are similar and operate in the same manner sothat the description and showing of gate 41 applies equally well togates 42, 43 and 44. Transistor 51 is an NPN type transistor includingan emitter 52, a base 53 and a collector 54. The emitter 52 is connectedto ground reference, base 53 is connected through a resistor 59 to anegative potential V3, and collector 54 is connected through a resistor61 to a first positive potential V1 and through a reverse biased diode63 to a second positive potential V2; that is, the anode of diode 63 isconnected to collector 54, and the cathode of diode 63 is connected toV2. An input signal is coupled from address decoder 69 through a resis'tor 60 to the base 53 of transistor 51.

Transistor 55 is a PNP type transistor including an emitter 56, a base57 and a collector 58. The emitter 56 is connected to the common line(for gate 41, emitter 56 is connected to line 31) to which the controlwindings of a column of cores are connected in parallel. The base 57 isconnected to the collector 54 of transistor 51, and through resistor 61to potential V1 and through diode 63 to potential V2. The collector 58is connected to a negative biasingpotential VP.

Transistor 51 is biased to normally be conducting. With transistor 51conducting, its collector 54 is essentially connected to groundpotential. A ground or zero potential is thus coupled to the base 57 oftransistor 55 causing transistor 55 to be conductive; emitter followeraction lowers the potential of the emitter 56 of transistor 55 toessentially ground potential. With transistor 55 conducting, anelectrical circuit is completed through the control winding of each ofthe cores in the column of cores associated therewith. For example, forthe control windings of the cores in column 1, a circuit is traceablefrom ground, parallel or common line 31, the control windings of thecores in column 1, the respective diodes, the emitter 56 to base 57 pathof transistor 55 and through the collector 54 to emitter 52 path oftransistor 51 to ground reference. When a complete electrical circuitfor a control winding is formed, the control winding'will, in essence,be short circuited and there will be a minimum transfer of energy fromthe associated primary winding to the associated secondary winding, aswill be explained hereinbelow.

To select a core, address decoder 69 activates the current driver forthe row of cores in which the core to be selected is positioned andprovides a negative potential to open the gate controlling the column ofcores in which the core to be selected is positioned. For purposes ofdescription, assume core 1A is to be selected. Address decoder 69activates current driver 23 and opens gate 41. The

operation of the circuitry is as follows: A negative poten tial coupledthrough resistor 60 to the base 53 of transistor 51 biases transistor 51to become nonconductive or cut off. When transistor 51 cuts off, diode63 is forward biased and clamps the potential at the base 57 oftransistor 55 at V2 which biases transistor 55 to cut off. Whentransistor .55 cuts off, the electrical circuit for the control windingsof the associated column of cores is open circuited until a potentialequal to V2 is established across the control winding at which pointtransistor 55 turns on, thus clamping the control potential at thislevel; that is, any higher voltage energy developed by the primarywinding is dissipated in the control winding. This, in turn, establishesa clamped voltage on the secondary windings NS of the associated columnof cores and provides a positive current control. Core 1A, positioned inthe row for which current driver 23 has been activated and alsopositioned in the column for which gate 41 has been opened, will providea predetermined transfer of energy from primary winding NP to thesecondary windings NS, as will be explained hereinbelow.

Referring now also to FIGS. 1a and lb, the secondary windings NS of eachof the cores in matrix 11 are connected in series with the inputwindings of groups of cores in a memory array.

In a first embodiment of the invention, as seen in FIG. In, each of thesecondary windings NS of the cores in matrix 11 are connected in serieswith a respective group of cores in the memory array and with a diodecircuit for purposes of reducing any undesired'current flow in thesecondary windings NS of the unselected cores when the control windingof the selected core is in its short circuit condition, for purposes tobe described below. Only seven of the cores of matrix 11 are shown sincethis is believed sufiiclent to an understanding the invention; it will,of course, be appreciated that the other cores of matrix 11 areconnected similarly to core groups in the memory array. One terminal ofeach of the secondary windings NS is connected to a common line 68, andthe other terminal of the secondary winding NS is connected in seriesthrough the windings of the cores in respective groups of the memoryarray. For example, one terminal of secondary winding NS of core 1A isconnected in series with core group 104 in the memory array. The lowerterminal, as oriented in FIG. 1a, of each of the memory array groupsdivides into two paths. For example, for group 104, the first path istraceable through a diode 88 and lead to the right-hand terminal, asoriented in FIG. 1a, of a resistor 99; the anode of diode 88 isconnected to the junction of the two paths and its cathode connected tolead 100 and resistor 99. The second path is traceable through a diode87 and lead to the lefthand terminal or resistor 99; the cathode ofdiode 87 is connected to the junction of the two paths and its anode isconnected to lead 110 and resistor 99. Diodes 82, 84, 86, 88, 90, 92 and94 associated with memory core groups 101, 102, 103, 104, 105, 106 and107, respectively, are connected in common to lead 100. Likewise, diodes81, 83, 85, 87, 89, 91 and 93, associated with memory core groups 101,102, 103, 104, 105, 106 and 107, respectively, are connected in commonto lead 110.

In a second embodiment of the invention, as seen in FIG. lb, each of thesecondary windings NS is connected in series with a respective group ofcores and a terminating resistor to ground reference. The secondarywinding NS of core 1A, for example, is connected through lead 74 inseries with a group of cores 104 in the memory array, and a terminatingresistor 114 to ground reference. Current flowing through each of thesecondary windings NS thus flows through the respective group of cores101, 102, 103, 104, 105, 106 or 107, and is dissipated in the respectiveterminating resistor 111, 112, 113, 114, 115, 116 or 117.

Ideally, when current is flowing through the control winding NC of theassociated core, the winding NC will be short circuited and no voltagewill be induced thereacross. All the current will thus flow through thecontrol winding and no current will flow in the associated secondary oroutput winding. Further, the impedance reflected back from the controlwinding NC to the associated primary winding NP will be zero; thus, novoltage will be reflected back by the control winding NC to the primarywinding or to the secondary winding.

It has, however, been found that even during the period when theassociated gates are closed and maximum current is flowing in thecontrol windings, that is, the winding is in essence, short circuited,the control windings together with the associated diode and thetransistor of the associated gate may still reflect a significantimpedance into the primary winding. For example, in core 1A, the controlwinding NC, diode 45 and transistors 51 and 55 in gate 41 may reflect asignificant impedance to the primary winding. The impedance of secondarywindings NS, the impedance of the windings on the cores of therespective memory array, and the impedance of any resistors in therespective lines are also reflected to the primary winding. This causesthe current flowing in the primary windings to divide between theassociated control winding and the secondary winding according to theratio of the reflected impedance. The ratio of the turns of the controlwinding and of the secondary winding are selected to provide a lowsecondary voltage.

The termination or circuit of FIG. 1b is satisfactory, for example, if,during the short circuited condition of the respective control winding,any current induced in the secondary windings NS which may flow throughthe respective drive line for a group of cores in the memory array isnot of sufficient magnitude to adversely affect the operation of thecores in the memory 'array. The foregoing condition may exist in sometwo dimensional arrays. In those two dimensional arrays in which thecurrent flowing in those drive lines not associated with the selectedcore is of sufiicient magnitude to adversely affect the operation of thememory cores; and, in the three dimensional arrays, the circuitry ofFIG. la is of specific importance. It has been found that in threedimensional arrays, the currents in the various drive lines normallytend to add to cause improper operation of the cores in the memoryarray.

The operation of the embodiment of FIG. 1a will now be' described. Asindicated above for simplicity in explanation, only a few of the coresof matrix 11 are shown in FIG. 1a; however, the operation as describedapplies to the overall matrix. Assume that core 1A of matrix 11 isselected and that a voltage VX is developed across the secondary windingNS; lead 74 connected to winding NS of core 1A will be at potential VX.Since the impedance of the windings of the memory array is relativelylow, the junction of diodes 87 and 88 is also essentially at potentialVX. Diode 88 will be for-ward biased and since it has a relatively lowforward impedance, lead 100 will also be essentially at potential VX.

As described above, to select core 1A, current driver 23 drives acurrent through line 13 and thus through the primary windings NP of allthe cores in row A. Each primary winding NP will also transfer an amountof energy to the associated secondary winding NS of all the other orunselected cores in row A. A voltage, designated as W, which is oflesser magnitude than voltage'VX will thus be developed across thesecondary winding NS of the unselected cores in row A, namely, in cores2A, 3A and 4A. Due to the relatively low impedance of the windings ofthe memory array groups 105, 106 and 107, the voltage VY appearing onleads 75, 76 and 77 will be impressed at the junction of diodes 8990,91--92 and 93-94, respectively. However, since diodes 90, 92 and 94 areconnected in common to line 100, as is diode 88 and since voltage VX isof a larger magnitude, that is, more positive, than voltage VY, diodes90, 92 and 94 will be reverse biased.

The current drivers associated with rows B, C, and D" are not activated,consequently, no current will be induced in the respective secondarywindings NS of the cores in these rows; therefore, the potential on thesecondary windings of the cores in these rows will be essentially zerovolts, designated as V0. Due to the relatively low impedance of thewindings in core groups 101, 102, and 103, the voltage V appearing onleads 71, 72 and 73 will be impressed at the unction of diodes 81-82,8384 and 85-86. Diodes 82, 84 and 86, which have their cathodesconnected to lead 100 and thus to potential VX will be reverse biased;however; diodes 81, 83 and 85 which have their anodes connected to lead110 will be forward biased. Current will flow from the more positivepotential VX to potential V0 through diode 88, lead 100 and resistor 99to lead 110; the current will then divide approximately evenly and flowthrough diodes 81, 83 and 85, the respective memory array groups 101,102 and 103, through leads 71, 72 and 73 and the respective secondarywindings of the cores in rows B, C and D to common line 68.

The voltage drop developed across resistor 99 causes the potential onlead 110 to be less than VY so that diodes 89, 91 and 93 are reversebiased and no current flows through the respective memory arrays 105,106 and 107. Thus, current is prevented from flowing in the secondarywindings NS of the cores, other than the selected core, in a row whichis energized by a current driver. The current flowing through each ofthe secondary windings in rows B, C and D is of a relatively very lowmagnitude and does not affect the operation of the cores in these rows.

The operation will, of course, be similar to the abov when any othercore in the matrix 11 is selected.

If the primary winding NP induces a negative potential in the leadconnecting the secondary windings NS to the respective memory arraygroups, the junction of the respective diodes will be at a negativepotential and current would tend to flow in the opposite direction ofthat stated above. However, the principle of operation of the circuit isthe same.

By insuring that the current flowing in the primary winding NP of theselected core is more than sutficient to supply the desired current inthe associated secondary winding NS, some current will always flowthrough the associated control winding NC. Since the wave shape of .thecurrent flowing in the control winding NC is of no consequence, thematerial from which the cores are made can have a non-rectangularhysteresis loop. Any drop which might occur in the current flowing inthe secondary winding NS can be made to occur almost entirely in thecontrol winding NC while the current is flowing in the secondary windingis clamped to essentially a square wave output.

If close regulation is desired during the reset cycle, that is, duringthe period when the cores shift their magnetic state during the readoperation; or, if suflicient flux is switched in the unselected coresduring the set cycle (during the writing operation) to provide anunacceptable amount of output energy upon resetting, a second group ofgates can be connected to each column of cores. This second group ofgates is similar to the gates 41-44 shown in FIG. 1a, and each gate ofthe second group is connected to a respective control winding inparallel to an associated one of gates 41-44. For the second group ofgates, the polarity of operation would vary between a minus voltage andground reference; therefore, the transistor corresponding to transistor55 would be an NPN type transistor with its emitter connected through acornmon line and a diode to the respective control winding; the diodewould have its cathode connected to the control winding and its anodeconnected to the respective transistor. The operation of the secondgroup of gates during the reset operation would be similar to that ofgates 41-44 during the set operation; as noted, the variation in voltageto operate the second group of gates would be opposite of that for gates41-44; that is, from a negative potential to ground rather than from apositive potential to ground.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:

1. A matrix comprising, in combination, a plurality of cores; a primary,a control and a secondary or output winding on each of said cores; meansselectively connected to said primary windings for energizing saidcores; a plurality of gating means each having first and secondconducting conditions; respective unilateral conducting means connectingone terminal of said control windings to an associated gating means, theother terminal of said control windings being connected to a referencepotential; each of said gating means being respectively connected to thecontrol windings of selected cores; means for selectively activating thegating means from the first to the second conducting conditions forrespectively completing and opening an electrical circuit for theassociated control windings; said gating means in a first conditionconnecting a voltage at said reference potential to said one terminal ofthe associated control windings for providing an effective zero biasacross said unilateral conducting means; the associated control windingthus being essentially short circuited to provide a counter energizationto said primary winding energization to thereby obtain an output signalon the associated output windings of a low magnitude; and said gatingmeans in second condition con- .necting a voltage of a second potentialto said unilateral conducting means for reverse biasing said unilateralconducting means; primary winding energization when above a selectedmagnitude causing a voltage to be developed across the associatedcontrol winding forforward biasing the associated ur|ilaiera1 conductingmeans to thereby permit current flow therethrough and hence provide acounter energizatidn for controllably clamping said output signal at asecond selected magnitude.

2. A matrix in accordance with claim 1 in which said unilateralconducting means are diodes.

3. A matrix in accordance with claim 1 in which said gating means areconnected in parallel to a column of cores, and in which primary energzing means are connected to the primary windings of a row of coreswhereby a core is selected to provide an output from its secondarywinding by energizing the' primary w ndings of an associated column ofcores and act vating an associated gating means to its second conductingcondition.

4. A matrix in accordance with claim 1 wherein each gating meanscomprises a pair of transistors biased to conduction in a firstconducting condition and blased to cut-oil in a second conductingcondition.

5. A matrix in accordance with claim 1 wherein said gating meanscomprises a pair of transistors each having base, emitter and collectorelectrodes; the base of the first of said transistors being connected tothe collector of the second'of said transistors; sources of operatingpotentials for said transistors; means for applying a first potential tothe base of said first transistor to cut-oft said first transistor; saidfirst transistor being biased to conduct when the voltage developedacross .the associated control winding overcomes the biasing effect ofsaid first potential and thereby clamps the voltage appearing acrosssaid secondary winding to said first potential; the electrical circuitfor the associated control windings being traceable through theemitter-to-base path of the first of said tran sistors and thecollector-toemitter path of the second of said transistors.

6. A matrix in accordance with claim 1 wherein each of said secondarywindings has one end connected to a reference line and its other endconnected in series with a terminal of the windings of a memory arrayarranged in groups; a diode connected to the other terminal of thewindings of each memory array group, a resistor connecting each of saiddiodes to a common line, current flowing through the secondary windingof a selected core and said resistor causing the diodes connected to thesecondary windings of the cores in an energized group to be reversebiased to thereby prevent current flow through the unselected cores ofan energized group and the respective memory array.

7. A matrix in accordance with claim 1 wherein each of said secondarywindings has one end connected to a reference line and its other endconnected in series with a terminal of the windings of a memory array; apair of diodes connected to form a parallel junction at the otherterminal of the windings of each memory array group; one diode of eachpair having its anode connected to said junction and its cathodeconnected to a first common line; the other diode of each pair havingits cathode connected to said junction and its anode connected to asecond common line; a resistor connecting said first and second commonlines, the voltage developed across the secondary winding of theselected core causing one of the diodes of each pair connected to theunselected cores to be reverse biased; current flowing through thesecondary winding of a selected core and said resistor reverse biasingthe other diode in each pair connected to the secondary windings of thecores in an energized group to thereby prevent current flow through theunselected cores of an energized group and the respective memory array;current flow through said resistor forward biasing the diodes connectedto the cores in the unenergized groups whereby current induced in thesecondary winding of the selected core divides and flows through saidforward biased diodes, the associated memory array windings and theassociated secondary windings to said reference line.

8. A matrix in accordance with claim 1 wherein said gating meanscomprises a first PNP type transistor and a second NPN type transistor,each having base, emitter and collector electrodes; biasing means forproviding operating potentials to said transistors; said firsttransistor having its emitter connected in parallel to the controlwindings of a core in each of said groups, its collector connected to afirst potential, and its base connected to the collector of said secondtransistor to receive the output signal therefrom; impedance meansconnecting the base of said first transistor to said biasing means forproviding a second potential to said base, the emitter of said secondtransistor being connected to ground reference; said biasing-meansnormally causing both said transistors to be conductive; means forconnecting an input signal to the base of said second transistor torender both said transistors nonconductive and thereby open said gatingmeans; said transistors remaining nonconductive until the voltagedeveloped across the associated control winding is of sufiicientmagnitude to raise the potential of the emitter of said first transistorto said second potential level whereby said transistors conduct and acircuit is completed for the associated control windings rwhereby anyenergy in excess of said second potential level is dissipated in saidcompleted circuit and whereby the voltage appearing across saidsecondary winding is clamped to a level determined by said secondpotential.

References Cited in the file of this patent UNITED STATES PATENTS1,309,494 Varley July '8, 1919 2,823,322 Trousdale Feb. 11, 19582,902,677 Counihan Sept. 1, 1959 2,933,618 Buck Apr. 19, 1960

1. A MATRIX COMPRISING, IN COMBINATION, A PLURALITY OF CORES; A PRIMARY,A CONTROL AND A SECONDARY OR OUTPUT WINDING ON EACH OF SAID CORES; MEANSSELECTIVELY CONNECTED TO SAID PRIMARY WINDINGS FOR ENERGIZING SAIDCORES; A PLURALITY OF GATING MEANS EACH HAVING FIRST AND SECONDCONDUCTING CONDITIONS; RESPECTIVE UNILATERAL CONDUCTING MEANS CONNECTINGONE TERMINAL OF SAID CONTROL WINDINGS TO AN ASSOCIATED GATING MEANS, THEOTHER TERMINAL OF SAID CONTROL WINDINGS BEING CONNECTED TO A REFERENCEPOTENTIAL; EACH OF SAID GATING MEANS BEING RESPECTIVELY CONNECTED TO THECONTROL WINDINGS OF SELECTED CORES; MEANS FOR SELECTIVELY ACTIVATING THEGATING MEANS FROM THE FIRST TO THE SECOND CONDUCTING CONDITIONS FORRESPECTIVELY COMPLETING AND OPENING AN ELECTRICAL CIRCUIT FOR THEASSOCIATED CONTROL WINDINGS; SAID GATING MEANS IN A FIRST CONDITIONCONNECTING A VOLTAGE AT SAID REFERENCE POTENTIAL TO SAID ONE TERMINAL OFTHE ASSOCIATED CONTROL WINDINGS FOR PROVIDING AN EFFECTIVE ZERO BIASACROSS SAID UNILATERAL CONDUCTING MEANS; THE ASSOCIATED CONTROL WINDINGTHUS BEING ESSENTIALLY SHORT CIRCUITED TO PROVIDE A COUNTER ENERGIZATIONTO SAID PRIMARY WINDING ENERGIZATION TO THEREBY OBTAIN AN OUTPUT SIGNALON THE ASSOCIATED OUTPUT WINDINGS OF A LOW MAGNITUDE; AND SAID GATINGMEANS IN SECOND CONDITION CON-